Data processor having multiple-buffer adapter between a system channel and an input/output bus
US4571671A · kind A · utility
46Cited by
1References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 13, 1983 |
| Grant date | Feb 18, 1986 |
| Priority date | — |
| Expiry date | May 13, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/122
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processor has a block-multiplexed system channel coupled to a processing engine and a byte-multiplexed bus coupled to multiple I/O devices. A multi-buffer adapter transfers data by cycle-steal (direct memory access) operations between the channel and the bus. The adapter has multiple buffers switchable to the channel in a burst mode by a channel interface and to the bus in a byte mode by a device-level interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.