Michael John Mayfield
25Patents
16h-index
31Co-inventors
81Inventor score
Filing activity: May 13, 1983 → Nov 5, 2004
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5737565A | System and method for diallocating stream from a stream buffer | Physics | 90 | Expired |
| US6574712B1 | Software prefetch system and method for predetermining amount of streamed data | Physics | 64 | Expired |
| US6460115B1 | System and method for prefetching data to multiple levels of cache including selectively using a software hint to override a hardware prefetch mechanism | Physics | 56 | Expired |
| US6085291A | System and method for selectively controlling fetching and prefetching of data to a processor | Physics | 46 | Expired |
| US4571671A | Data processor having multiple-buffer adapter between a system channel and an input/output bus | Physics | 46 | Expired |
| US5740399A | Modified L1/L2 cache inclusion for aggressive prefetch | Physics | 45 | Expired |
| US5758119A | System and method for indicating that a processor has prefetched data into a primary cache and not into a secondary cache | Physics | 43 | Expired |
| US6446167B1 | Cache prefetching of L2 and L3 | Physics | 39 | Expired |
| US5623632A | System and method for improving multilevel cache performance in a multiprocessing system | Physics | 32 | Expired |
| US5664147A | System and method that progressively prefetches additional lines to a distributed stream buffer as the sequentiality of the memory accessing is demonstrated | Physics | 32 | Expired |
| US6915415B2 | Method and apparatus for mapping software prefetch instructions to hardware prefetch logic | Physics | 27 | Expired |
| US5721864A | Prefetching instructions between caches | Physics | 27 | Expired |
| US5787478A | Method and system for implementing a cache coherency mechanism for utilization within a non-inclusive cache memory hierarchy | Physics | 25 | Expired |
| US6535962B1 | System and method for prefetching data using a hardware prefetch mechanism | Physics | 24 | Expired |
| US6578130B2 | Programmable data prefetch pacing | Physics | 19 | Expired |
| US5809529A | Prefetching of committed instructions from a memory to an instruction cache | Physics | 17 | Expired |
| US5860150A | Instruction pre-fetching of a cache line within a processor | Physics | 13 | Expired |
| US6202128A | Method and system for pre-fetch cache interrogation using snoop port | Physics | 13 | Expired |
| US6968431B2 | Method and apparatus for livelock prevention in a multiprocessor system | Physics | 13 | Expired |
| US7305526B2 | Method, system, and program for transferring data directed to virtual memory addresses to a device memory | Physics | 10 | Expired |
| US6446170B1 | Efficient store machine in cache based microprocessor | Physics | 9 | Expired |
| US6178493A | Multiprocessor stalled store detection | Physics | 8 | Expired |
| US6587930B1 | Method and system for implementing remstat protocol under inclusion and non-inclusion of L1 data in L2 cache to prevent read-read deadlock | Physics | 2 | Expired |
| US6298417A | Pipelined cache memory deallocation and storeback | Physics | 1 | Expired |
| US7171445B2 | Fixed snoop response time for source-clocked multiprocessor busses | Physics | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.