N- well CMOS process on a P substrate with double field guard rings and a PMOS buried channel

US4574467A · kind A · utility

Assignee

• Solid State Scientific Corporation · US

Inventors

• Mark A. Halfacre · Horsham, US
• David S. Pan · Doylestown, US
• Wing K. Huie · North Wales, US

Key dates

• Filing date: Aug 31, 1983
• Grant date: Mar 11, 1986
• Expiry date: Aug 31, 2003

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0191

Abstract

CMOS transistors are fabricated in a P substrate using N- well regions. These wells are positioned to prevent aluminum spiking in the N channel devices. After P guard rings are formed for both P and N channel devices, additional masking and implantation are performed to produce N guard rings in the P channel devices. Before the transistors are formed, an implantation of P type impurities is performed causing the P channel devices, when they are formed, to have a PMOS buried channel.