David S. Pan
10Patents
8h-index
11Co-inventors
65Inventor score
Filing activity: Jul 29, 1981 → Nov 14, 1995
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5621813A | Pattern recognition alignment system | Physics | 39 | Expired |
| US4385947A | Method for fabricating CMOS in P substrate with single guard ring using local oxidation | Electricity | 35 | Expired |
| US4574467A | N- well CMOS process on a P substrate with double field guard rings and a PMOS buried channel | Electricity | 34 | Expired |
| US4598460A | Method of making a CMOS EPROM with independently selectable thresholds | Electricity | 33 | Expired |
| US4590665A | Method for double doping sources and drains in an EPROM | Emerging Cross-Sectional Technologies | 26 | Expired |
| US4914051A | Method for making a vertical power DMOS transistor with small signal bipolar transistors | Emerging Cross-Sectional Technologies | 23 | Expired |
| US4774202A | Memory device with interconnected polysilicon layers and method for making | Electricity | 22 | Expired |
| US4646425A | Method for making a self-aligned CMOS EPROM wherein the EPROM floating gate and CMOS gates are made from one polysilicon layer | Electricity | 22 | Expired |
| US5045492A | Method of making integrated circuit with high current transistor and CMOS transistors | Emerging Cross-Sectional Technologies | 7 | Expired |
| US4706102A | Memory device with interconnected polysilicon layers and method for making | Electricity | 6 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.