Method of manufacturing an insulated-gate field-effect transistor
US4575920A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 2, 1984 |
| Grant date | Mar 18, 1986 |
| Priority date | — |
| Expiry date | May 2, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/662
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing an insulated-gate field-effect transistor on a silicon substrate at high density for large scale integration is disclosed. The source and drain regions of the transistor are formed by implanting low density impurity ions into the silicon substrate and then heating the substrate at a temperature in the range of 900.degree. to 1300.degree. C. Thereafter, additional ions are implanted into the source and drain regions, and the substrate is heated at a second temperature of 700.degree. C., or lower, to provide good ohmic contact between metal electrodes and the source and drain regions. In addition, the sheet resistivity of the source and drain regions is small so that high speed operation of the transistor is achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.