Memory correction scheme using spare arrays
US4584681A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 1983 |
| Grant date | Apr 22, 1986 |
| Priority date | — |
| Expiry date | Sep 2, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Spare chips are employed together with a replacement algorithm to replace chips in memory array when failure is generally more extensive then unrelated cell fails in the memory chips. That is, substitution will be made if an error condition is a result of the failure of a whole chip (chip-kill), a segment of a chip (island-kill), a column of bits of a chip or a row of bits of a chip but will not be performed when it is due to a single failed cell. The replacement of a chip with a chip-kill or with an island-kill is done on the fly and involves only a row of the memory chips or elements leaving other elements of the memory unaffected by the replacement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.