Semiconductor memory device
US4586167A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 1984 |
| Grant date | Apr 29, 1986 |
| Priority date | — |
| Expiry date | Jan 4, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a semiconductor memory device which is operable in a selected one of page mode and nibble mode, depending upon the length of time in which an external column address strobe signal stays at a specific level. The semiconductor memory device comprises a circuit for discriminating the length of time where the external column address strobe signal is at a specific level with a predetermined period of time. Data is outputted in page mode in response to one of results of such discrimination and in nibble mode in response to the other result of the discrimination. The discriminating circuit may comprise a second internal column address strobe signal generator and a delay circuit. The second internal column address strobe signal generator includes a NAND circuit at its first stage, and the delay circuit is designed to have different delay times at the building-up and downward edges of an input signal applied thereto. The output of the discriminator is used to operate and reset an output circuit whereby one of the output modes is selected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.