Process for the manufacture of a self-aligned thin-film transistor
US4587720A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 1984 |
| Grant date | May 13, 1986 |
| Priority date | — |
| Expiry date | Oct 10, 2004 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/949
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The process consists in producing the grid (4) of the transistor on a glass substrate (2), depositing an insulating layer (6) on the substrate and grid, depositing a thick layer (8) of hydrogenated amorphous silicon on the insulating layer, depositing on the silicon layer a layer (10) of positive photosensitive resin sensitive to light of a wavelength greater than 550 nm, irradiating the resin layer through the substrate, the grid serving as a mask for the irradiation, developing the resin, etching the silicon layer until the insulating layer is bared, the remanent resin serving as a mask for the etching, depositing the layers permitting the making of the electrical contacts and the electrodes of the source and of the drain, eliminating the remanent resin (10a), and etching the electrodes of the source and of the drain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.