Method for double doping sources and drains in an EPROM
US4590665A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 1984 |
| Grant date | May 27, 1986 |
| Priority date | — |
| Expiry date | Dec 10, 2004 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/082
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A CMOS EPROM or the like is made wherein the basic memory device or EPROM device is an N-channel IGFET (insulated gate field effect transistor) having a control gate self-aligned with an underlying floating gate. The sources and drains of the EPROM devices as well as the sources and drains of peripheral N-channel transistors, are made by implanting with arsenic and with phosphorous. When heated, the faster diffusing phosphorous outruns, and extends from the bulk of, the arsenic so that these sources and drains extend slightly under the adjacent gate. This extension of the drain in the memory device enables a faster programming capability. A similar but oppositely directed lateral extension of all these sources and drains reduces the leakage to the substrate and reduces the chances of shorts to the substrate due to slightly misaligned metal to source and drain contacts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.