Simultaneous placement and wiring for VLSI chips
US4593363A · kind A · utility
154Cited by
11References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 12, 1983 |
| Grant date | Jun 3, 1986 |
| Priority date | — |
| Expiry date | Aug 12, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
For designing the layout of a master-slice VLSI chip steps for placing components and for determining the wiring pattern interconnecting them are alternated in an iterative process. The chip area is partitioned into subareas of decreasing size, the set of components is partitioned into subsets which fit to the respective subareas, and after each partitioning step the global wiring is determined for the existing subnets of the whole network. Due to this interrelation of placement and wiring procedures, advantages with respect to total wire length, overflow number of wires, and processing time can be gained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.