Inventor · Cupertino, CA, US

Michael Burstein

11Patents
5h-index
8Co-inventors
59Inventor score

Filing activity: Aug 12, 1983 → Mar 7, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US7992122B1 Method of placing and routing for power optimization and timing closure Physics 184 Active
US4593363A Simultaneous placement and wiring for VLSI chips Physics 154 Expired
US8370786B1 Methods and software for placement improvement based on global routing Physics 10 Active
US8015533B1 Method for matching timing on high fanout signal paths using routing guides Physics 9 Active
US7260804B1 Method for circuit block routing based on switching activity Physics 9 Expired
US7360193B1 Method for circuit block placement and circuit block arrangement based on switching activity Physics 5 Expired
US8185860B2 Method for matching timing on high fanout signal paths using routing guides Physics 3 Active
US8468488B1 Methods of automatically placing and routing for timing improvement Physics 3 Active
US8549450B1 Methods and software for determining net bounds for placing and routing Physics 2 Active
US11270449B2 Method and system for location detection of photographs using topographic techniques Physics 1 Active
US11798181B2 Method and system for location detection of photographs using topographic techniques Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.