Method of making a CMOS EPROM with independently selectable thresholds

US4598460A · kind A · utility

Assignee

• Solid State Scientific Corporation · US

Inventors

• Alexander H. Owens · Los Gatos, US
• Mark A. Halfacre · Horsham, US
• David S. Pan · Doylestown, US

Key dates

• Filing date: Dec 10, 1984
• Grant date: Jul 8, 1986
• Expiry date: Dec 10, 2004

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

A process for making an integrated cirucit EPROM having an array of EPROM devices and CMOS peripheral circuits, including blanket depositions of a first and a second polysilicon layers on a silicon substrate and removing portions of those polysilicon layers. The EPROM floating gate is made from the first polysilicon layer, and the EPROM control gate as well as the P-channel and N-channel gates of the peripheral transistors are all made from the second polysilicon layer. Independently adjustable thresholds for each of the three device types are made possible by forming an N-well at the substrate region at which the P-channel device is to be built, blanket implanting all three channels prior to selectively forming the first polysilicon layer over the EPROM region, and then selectively doping the channels of the N- and P-channel devices only.