Nonvolatile electrically alterable memory
US4599706A · kind A · utility
42Cited by
4References
29Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 14, 1985 |
| Grant date | Jul 8, 1986 |
| Priority date | — |
| Expiry date | May 14, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A compact, floating gate, nonvolatile, electrically alterable memory device is fabricated with three layers of polysilicon. In a nonvolatile memory array, each cell is electrically isolated from other cells to eliminate data disturb conditions in nonaddressed cells of the memory array. The memory cell and array is described in a first embodiment as including four electrode layers, one of which being formed as a substrate coupling electrode. A second embodiment includes a three electrode layer device wherein the need for the substrate coupling electrode is eliminated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.