Process of making twin well VLSI CMOS
US4599789A · kind A · utility
65Cited by
17References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 15, 1984 |
| Grant date | Jul 15, 1986 |
| Priority date | — |
| Expiry date | Jun 15, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/859
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
CMOS devices are formed in self-aligned wells in a substrate produced by a two mask, one photolithographic step process wherein the first mask is used as a template to form the second inverse mask of substantially equal thickness. The gates are used as alignment mask for shallow source and drain regions and subsequently formed lateral gate spacers are used as alignment mask for deep source and drain regions. Exposed source and drain regions and silicon gates have silicide formed thereon by a non-selective process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.