John T. Gasner
25Patents
10h-index
34Co-inventors
75Inventor score
Filing activity: Sep 21, 1977 → Dec 31, 2013
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US4599789A | Process of making twin well VLSI CMOS | Electricity | 65 | Expired |
| US4760433A | ESD protection transistors | Electricity | 53 | Expired |
| US5547896A | Direct etch for thin film resistor using a hard mask | Emerging Cross-Sectional Technologies | 40 | Expired |
| US4666737A | Via metallization using metal fillets | Electricity | 39 | Expired |
| US5481129A | Analog-to-digital converter | Electricity | 26 | Expired |
| US4135955A | Process for fabricating high voltage CMOS with self-aligned guard rings utilizing selective diffusion and local oxidation | Emerging Cross-Sectional Technologies | 24 | Expired |
| US5650344A | Method of making non-uniformly nitrided gate oxide | Emerging Cross-Sectional Technologies | 22 | Expired |
| US4578859A | Implant mask reversal process | Emerging Cross-Sectional Technologies | 12 | Expired |
| US5808348A | Non-uniformly nitrided gate oxide and method | Emerging Cross-Sectional Technologies | 11 | Expired |
| US5648678A | Programmable element in barrier metal device | Emerging Cross-Sectional Technologies | 11 | Expired |
| US4223334A | High voltage CMOS with local oxidation for self-aligned guard rings and process of fabrication | Electricity | 9 | Expired |
| US7005369B2 | Active area bonding compatible high current structures | Electricity | 6 | Expired |
| US5696452A | Arrangement and method for improving room-temperature testability of CMOS integrated circuits optimized for cryogenic temperature operation | Physics | 6 | Expired |
| US8536044B2 | Protecting bond pad for subsequent processing | Electricity | 4 | Active |
| US7224074B2 | Active area bonding compatible high current structures | Electricity | 3 | Expired |
| US6350640B1 | CMOS integrated circuit architecture incorporating deep implanted emitter region to form auxiliary bipolar transistor | Electricity | 3 | Expired |
| US8274160B2 | Active area bonding compatible high current structures | Electricity | 3 | Active |
| US8963266B2 | Devices including bond pad having protective sidewall seal | Electricity | 3 | Active |
| US7795130B2 | Active area bonding compatible high current structures | Electricity | 3 | Active |
| US7341958B2 | Integrated process for thin film resistors with silicides | Electricity | 3 | Expired |
| US7662692B2 | Integrated process for thin film resistors with silicides | Electricity | 1 | Active |
| US8569896B2 | Active area bonding compatible high current structures | Electricity | 0 | Active |
| US8946912B2 | Active area bonding compatible high current structures | Electricity | 0 | Active |
| US8652960B2 | Active area bonding compatible high current structures | Electricity | 0 | Active |
| US8338914B2 | Integrated process for thin film resistors with silicides | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.