Personalizable masterslice substrate for semiconductor chips
US4602271A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 1984 |
| Grant date | Jul 22, 1986 |
| Priority date | — |
| Expiry date | Feb 15, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15174
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A substrate for packaging semiconductor chips is provided which is structured with conductors having opposite ends terminating in a mounting surface and intermediate portions extending beneath the surface. The ends of the conductors are arranged in repeating patterns longitudinally along the substrate separated by orthogonal strips free of conductor ends to allow for dense surface wiring. The repeating patterns are arranged to allow for chip mounting sites having sufficient spacing to allow for surface wiring. In this way chips in the same and repeat pattern can be connected by personalized surface wiring and preset substrate conductors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.