Data output circuit for dynamic memory device
US4603403A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 16, 1984 |
| Grant date | Jul 29, 1986 |
| Priority date | — |
| Expiry date | May 16, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Data from a latch section for latching the contents in a plurality of memory cells are selectively applied to a data output section through paired output lines. In the data output section, immediately before the data is output, the nodes providing gate inputs to a load transistor and a drive transistor are connected to a signal for driving the output section and become at ground level. The output of the data, which is the same as that produced in the previous cycle, is continued till the start of a cycle in which the data from the latch section is output to the output line pair. At the start of a cycle in which new data is applied from the output line pair, a reset operation is performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.