Method for making a CMOS circuit having a reduced tendency to latch by controlling the band-gap of source and drain regions
US4603471A · kind A · utility
13Cited by
4References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 6, 1984 |
| Grant date | Aug 5, 1986 |
| Priority date | — |
| Expiry date | Sep 6, 2004 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/918
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The tendency of a CMOS circuit to latch up is reduced by implanting ions of germanium or tin into the source and drain regions of the circuit. The low energy gap of these ions lowers the band gap of the source and drain regions, which in turn inhibits their ability to inject carriers into the substrate and well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.