Self-aligned metal structure for integrated circuits
US4608589A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 1983 |
| Grant date | Aug 26, 1986 |
| Priority date | — |
| Expiry date | Jul 11, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/20
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A self-aligned metal integrated circuit structure is described which achieves self-aligned metal to silicon contacts and sub-micron contact-to-contact and metal-to-metal spacing. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal and dielectric structure is substantially planar. The method for forming this structure involves providing a silicon body and then forming a first insulating layer on a major surface of the silicon body. A layer of polycrystalline silicon is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. A second insulating layer is then formed on both the substantially horizontal surfaces and substantially vertical surfaces. Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions on the major surface of the silicon body. The remaining polycrystalline silicon layer is then removed by etching to leave the nar…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.