Error checking and correction circuitry for use with an electrically-programmable and electrically-erasable memory array
US4612640A · kind A · utility
69Cited by
11References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 21, 1984 |
| Grant date | Sep 16, 1986 |
| Priority date | — |
| Expiry date | Feb 21, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An on-chip checking and correction circuit extends the program/erase endurance of a semi-conductor memory array and catches data retention failures in individual memory cells of the array. For each data byte in the memory array, four parity bits are computed using a modified Hamming Code and stored in additional bit cells associated with that data byte. During read and write operations, check bits are calculated using the same Hamming Code and used to correct single-bit errors; error checking and correction is repeated if necessary up to a predetermined number of tries.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.