Hybrid extended drain concept for reduced hot electron effect
US4613882A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 1985 |
| Grant date | Sep 23, 1986 |
| Priority date | — |
| Expiry date | Apr 12, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
Abstract
Hot electron injection into the gate oxides of MOSFET devices imposes limitations on the miniaturization of such devices in VLSI circuits. A buried channel with a surface spacer is provided to guard against hot electron trapping effects while preserving process and structure compatibility with micron or submicron VLSI devices. The channel current is redirected into a buried channel at a distance away from the interface in the vicinity of the drain region where the hot electron effect is most likely to occur. Additionally, a surface implant is performed to improve any gate control that may be lost as a result of the buried channel so as to mitigate any degradation of the current-voltage characteristics of the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.