Packaging microminiature devices
US4613891A · kind A · utility
40Cited by
9References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 17, 1984 |
| Grant date | Sep 23, 1986 |
| Priority date | — |
| Expiry date | Feb 17, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One or more silicon-integrated-circuit chips are attached, active side up, to the bottom side of a silicon wafer. A sloped-wall through-aperture is etched in the wafer in registry with a portion of the active side of each attached chip. A lithographically defined conductive pattern is then formed on the top side of the wafer and on the sloped walls to connect conductive pads on each chip to conductive pads on other chips and/or to conductive terminals disposed along the periphery of the wafer. The resulting packaged chip assembly has advantageous performance and cost characteristics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.