Gate array chip
US4613958A · kind A · utility
8Cited by
10References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 28, 1984 |
| Grant date | Sep 23, 1986 |
| Priority date | — |
| Expiry date | Jun 28, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/901
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is a memory cell circuit for a gate array. The memory cell circuit is D.C. testable and has particular utility when employed in an integrated circuit containing "a mix of logic and array". Also disclosed is a memory array particularly adapted for use in an integrated circuit containing TTL logic circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.