Multi-port system
US4616347A · kind A · utility
24Cited by
8References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 31, 1983 |
| Grant date | Oct 7, 1986 |
| Priority date | — |
| Expiry date | May 31, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is especially directed towards an improved support circuitry for a memory array which utilizes support circuitry in a memory array such that, when an address compare occurs, selected ones of the array word decoders are disabled to prevent a multiple read, and selected higher order read heads are altered, i.e., inhibited from reading the output data of the higher order bit lines and forced to read or copy the lowest order bit lines having the same address as the uninhibited word decoder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.