Kerry Bernstein
143Patents
19h-index
123Co-inventors
89Inventor score
Filing activity: May 31, 1983 → Dec 16, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7692944B2 | 3-dimensional integrated circuit architecture, structure and method for fabrication thereof | Electricity | 253 | Active |
| US7115920B2 | FinFET transistor and circuit | Electricity | 163 | Expired |
| US6326666A | DTCMOS circuit having improved speed | Electricity | 125 | Expired |
| US7605429B2 | Hybrid crystal orientation CMOS structure for adaptive well biasing and for power and performance enhancement | Electricity | 122 | Expired |
| US7750682B2 | CMOS back-gated keeper technique | Electricity | 120 | Active |
| US7183142B2 | FinFETs with long gate length at high density | Electricity | 46 | Expired |
| US6677637B2 | Intralevel decoupling capacitor, method of manufacture and testing circuit of the same | Emerging Cross-Sectional Technologies | 46 | Expired |
| US6236103A | Integrated high-performance decoupling capacitor and heat sink | Electricity | 43 | Expired |
| US6433587B1 | SOI CMOS dynamic circuits having threshold voltage control | Electricity | 41 | Expired |
| US6882015B2 | Intralevel decoupling capacitor, method of manufacture and testing circuit of the same | Emerging Cross-Sectional Technologies | 30 | Expired |
| US6452251B1 | Damascene metal capacitor | Electricity | 26 | Expired |
| US4616347A | Multi-port system | Physics | 24 | Expired |
| US8055822B2 | Multicore processor having storage for core-specific operational data | Physics | 24 | Active |
| US7285477B1 | Dual wired integrated circuit chips | Electricity | 24 | Expired |
| US7928548B2 | Silicon heat spreader mounted in-plane with a heat source and method therefor | Electricity | 23 | Active |
| US6548338B2 | Integrated high-performance decoupling capacitor and heat sink | Electricity | 23 | Expired |
| US6956417B2 | Leakage compensation circuit | Electricity | 23 | Expired |
| US6954916B2 | Methodology for fixing Qcrit at design timing impact | Physics | 21 | Expired |
| US6794901B2 | Apparatus for reducing soft errors in dynamic circuits | Electricity | 20 | Expired |
| US6523159B2 | Method for adding decoupling capacitance during integrated circuit design | Physics | 18 | Expired |
| US7195971B2 | Method of manufacturing an intralevel decoupling capacitor | Emerging Cross-Sectional Technologies | 16 | Expired |
| US7629233B2 | Hybrid crystal orientation CMOS structure for adaptive well biasing and for power and performance enhancement | Electricity | 16 | Active |
| US7521950B2 | Wafer level I/O test and repair enabled by I/O layer | Physics | 16 | Active |
| US7913202B2 | Wafer level I/O test, repair and/or customization enabled by I/O layer | Physics | 16 | Active |
| US8013342B2 | Double-sided integrated circuit chips | Electricity | 16 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.