Redundancy circuit for use in a semiconductor memory array
US4617651A · kind A · utility
53Cited by
3References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 22, 1984 |
| Grant date | Oct 14, 1986 |
| Priority date | — |
| Expiry date | Feb 22, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/785
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory circuit having primary and redundant arrays with the capability of substituting the redundant arrays for defective primary arrays by address location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.