Polymerizable planarization layer for integrated circuit structures
US4619837A · kind A · utility
7Cited by
6References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 1, 1985 |
| Grant date | Oct 28, 1986 |
| Priority date | — |
| Expiry date | Feb 1, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention comprises an improvement in the process of manufacturing an integrated circuit structure having stepped topography which comprises coating the integrated circuit structure with a polymerizable material in the substantial absence of a solvent and then polymerizing the material to provide a substantially planar surface on the integrated circuit structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.