High performance, small area thin film transistor
US4620208A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 1983 |
| Grant date | Oct 28, 1986 |
| Priority date | — |
| Expiry date | Nov 8, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6728
Abstract
A high performance, small area thin film transistor has a drain region, an insulating layer, and a source region at least portions of the edge of which form a non-coplanar surface with respect to a substrate. The insulative layer is formed in between the source and drain regions. A deposited semiconductor overlies the non-coplanar surface to form a current conduction channel between the drain and source. A gate insulator and gate electrode overly at least a portion of the deposited semiconductor adjacent thereto. The length of the current conduction channel is determined by the thickness of the insulative layer and therefore can be made short without precision photolithography. The non-coplanar surface can be formed by utilizing a dry process to simultaneously etch through several layers in a continuous one-step process. A second dielectric layer may be formed above the three previous layers. This decouples the gate electrode from the source region by creating two capacitances in series, thereby limiting further the capacitance between the gate electrode and the source region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.