MOS rear end processing
US4620986A · kind A · utility
27Cited by
13References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 15, 1985 |
| Grant date | Nov 4, 1986 |
| Priority date | — |
| Expiry date | Oct 15, 2005 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/958
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for the reduction of defect formation in conductive layers of semiconductor bodies during patterning, alloying and passivation. A film of low temperature spin-on-glass containing dye is formed on the conductive layer prior to patterning and any high temperature process greater than 200 degrees C. Hermetic passivation is achieved by depositing on the conductive layer a composite film consisting of a lower, tensile layer and an upper, compressive layer with the net force of the passivation film being tensile.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.