Soft error protection circuit for a storage cell
US4621345A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 1984 |
| Grant date | Nov 4, 1986 |
| Priority date | — |
| Expiry date | Dec 17, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0375
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A soft error protection circuit is disclosed for a storage cell, such as a latch having a first input/output node and a second input/output node which are respectively connected to a charging source, the first node being selectively charged at least during a write interval, to represent a stored, first binary logic state for the latch. The circuit includes an insulated gate, field effect capacitor having a diffusion electrode connected to the second node and having a gate electrode, for selectively loading the second node with an additional capacitance. An inverter circuit has an input connected to the second node and an output connected to the gate electrode of the capacitor, for applying a capacitance enhancing bias to the gate electrode in at least a read interval following the write interval, when the first binary logic state has been stored in the latch, to apply the additional capacitance to the second node. The charging source supplies charge to both the first node and the second node at least following a soft error event which has caused the first node to become at least partially discharged during the read interval. In accordance with the invention, the additional capacita…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.