Digital signal level translation/master-slave flip flop with look-ahead
US4626706A · kind A · utility
6Cited by
1References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 24, 1984 |
| Grant date | Dec 2, 1986 |
| Priority date | — |
| Expiry date | May 24, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/289
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is a digital signal translation circuit for translating a first type signal to a second type signal which comprises a master latch and a slave latch. The master latch latches the incoming first type signal during a first portion of the clock signal. A slave latch latches the master latch output and generates a differential output. The differential output of the slave drives an output driver circuit which generates the second type signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.