Sense amplifier with reduced instantaneous power
US4627033A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 1984 |
| Grant date | Dec 2, 1986 |
| Priority date | — |
| Expiry date | Aug 2, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4091
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A CMOS sense amplifier circuit for a dynamic read/write memory employs cross-coupled N-channel transistors and cross-coupled P-channel transistors, returned to the voltage supply and ground through two separate sets of P and N channel transistors selectively activated by sense clocks. The return transistors are activated for either fast or slow sensing, depending upon the address input. The selected columns are sensed at maximum speed, and non-selected columns which are only being refreshed are sensed at a slower speed. A large return transistor is switched into the circuit only for fast sensing, and other smaller transistors perform the slow sense function with high resistance returns to the supply so peak current is lower. The current needed to charge and discharge the bit lines is thus spread out, and the peak current is decreased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.