Stacked semiconductor memory
US4633438A · kind A · utility
40Cited by
1References
10Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Dec 13, 1984 |
| Grant date | Dec 30, 1986 |
| Priority date | — |
| Expiry date | Dec 13, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a 3-transistor random access memory for dynamic operation, the invention discloses a structure in which one of the transistors is stacked on the other transistor. A transistor for writing is disposed on a transistor for reading, and one of its terminals is used in common with the gate electrode of a transistor for judging data. The other terminal is connected to one of the terminals of the transistor for reading. A memory cell capable of extremely large scale integration can be obtained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.