Tapered groove IC isolation
US4635090A · kind A · utility
37Cited by
6References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 13, 1985 |
| Grant date | Jan 6, 1987 |
| Priority date | — |
| Expiry date | May 13, 2005 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/168
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device and the method of manufacturing the same are disclosed, the semiconductor device having a plurality of elements isolated by a groove having a gentle slope at the upper side wall, and a steep slope at the lower side wall. This groove provides low steps on its mouth and occupies a small area on the substrate, thus enabling an extremely high-density integrated circuit to be formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.