Memory array biasing circuit for high speed CMOS device
US4636983A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 1984 |
| Grant date | Jan 13, 1987 |
| Priority date | — |
| Expiry date | Dec 20, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A current limiting, process compensating circuit for CMOS memory arrays is provided. A dual transistor bias circuit is connected to each of a pair of columns of the array with a four transistor voltage reference circuit having its output connected to the gates of the active P-channel transistor of each bias circuit. A first P-channel transistor of the voltage reference circuit is sized to be less than the P-channel transistor of the bias circuit and the other three N-channel transistors are sized to be the same as the second transistor of the bias circuit and the two transistors of each memory cell in the array. As supply voltage to the array moves up or down making more or less current available, the combined circuit maintains nearly constant current on the first transistor of each bias circuit while compensating for process variation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.