Bruce L. Bateman
67Patents
11h-index
21Co-inventors
78Inventor score
Filing activity: Dec 20, 1984 → Jun 14, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8937292B2 | Vertical cross point arrays for ultra high density memory applications | Electricity | 57 | Active |
| US6378060B1 | System to implement a cross-bar switch of a broadband processor | Physics | 34 | Expired |
| US8891276B2 | Memory array with local bitlines and local-to-global bitline pass gates and gain stages | Physics | 33 | Active |
| US8943119B2 | System and method to implement a matrix multiply unit of a broadband processor | Physics | 27 | Active |
| US7738274B1 | Content-addressable memory architecture | Physics | 26 | Active |
| US4636983A | Memory array biasing circuit for high speed CMOS device | Physics | 25 | Expired |
| US7800287B2 | Enhanced emission from pc-LEDs using IF filters | Physics | 19 | Active |
| US9117495B2 | Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations | Physics | 18 | Active |
| US9449669B2 | Cross-coupled thyristor SRAM circuits and methods of operation | Electricity | 13 | Active |
| US9390796B2 | Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations | Physics | 13 | Active |
| US8195735B2 | System and method to implement a matrix multiply unit of a broadband processor | Physics | 12 | Active |
| US9691480B2 | Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations | Physics | 11 | Active |
| US9312307B2 | Vertical cross point arrays for ultra high density memory applications | Electricity | 11 | Active |
| US9496020B2 | Six-transistor thyristor SRAM circuits and methods of operation | Electricity | 10 | Active |
| US9653151B1 | Memory array having segmented row addressed page registers | Electricity | 10 | Active |
| US9564441B2 | Two-transistor SRAM semiconductor structure and methods of fabrication | Electricity | 9 | Active |
| US8610099B2 | Planar resistive memory integration | Electricity | 9 | Active |
| US9564198B2 | Six-transistor SRAM semiconductor structures and methods of fabrication | Electricity | 9 | Active |
| US5535166A | Circuit for isolating and driving interconnect lines | Physics | 9 | Expired |
| US9460771B2 | Two-transistor thyristor SRAM circuit and methods of operation | Electricity | 8 | Active |
| US7096144B1 | Digital signal sampler | Physics | 8 | Expired |
| US9564199B2 | Methods of reading and writing data in a thyristor random access memory | Electricity | 7 | Active |
| US9419217B2 | Vertical cross-point memory arrays | Electricity | 7 | Active |
| US9029827B2 | Planar resistive memory integration | Electricity | 6 | Active |
| US8737151B2 | Low read current architecture for memory | Physics | 6 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.