Summation of address transition signals
US4636991A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 1985 |
| Grant date | Jan 13, 1987 |
| Priority date | — |
| Expiry date | Aug 16, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit, in using address transition detection to equilibrate bit lines, generates a summation address transition signal for the row address as well as a summation address transition signal for the column address. There is a transition detector for each address signal. The outputs of the transition detectors for the row address signals are summed in at least two logic stages using CMOS logic gates to generate the summation address signal for the row address. Similarly, the outputs of the transition detectors for the column address signals are summed in at least two logic stages using CMOS logic gates to generate the summation address signal for the column address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.