Method of making precision high-value MOS capacitors
US4639274A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 28, 1984 |
| Grant date | Jan 27, 1987 |
| Priority date | — |
| Expiry date | Nov 28, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/321
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for producing an improved capacitor in MOS technology utilizing a thin layer oxide dielectric to improve the active/parasitic capacitance ratio while maintaining a high breakdown voltage and a low leakage current. A polycrystalline silicon layer is formed over a silicon dioxide field region on a wafer of semiconductor silicon. Phosphorus ions are implanted in the polycrystalline silicon layer at an implant energy between approximately 80 and 100 keV. The surface of the polycrystalline silicon layer is oxidized to form an interpoly oxide, utilizing an oxidation temperature which, for the implant dosage of phosphorus ions used, is sufficient to make the interpoly oxide layer approximately 770 Angstroms thick. The structure is then annealed at a temperature of approximately 1100.degree. C. in oxygen and HCl. A second polycrystalline silicon layer is formed over the interpoly oxide layer, and the process completed in the conventional manner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.