Self-aligned split gate EPROM
US4639893A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 15, 1984 |
| Grant date | Jan 27, 1987 |
| Priority date | — |
| Expiry date | May 15, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A self-aligned split gate single transistor memory cell structure is formed by a process which self aligns the drain region to one edge of a floating gate. The portion of the channel underneath the floating gate is accurately defined by using one edge of the floating gate to align the drain region. The control gate formed over the floating gate controls the portion of the channel region between the floating gate and the source to provide split gate operation. The source region is formed sufficiently far from the floating gate so that the channel length between the source region and the closest edge of the floating gate is controlled by the control gate but does not have to be accurately defined.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.