Planarization of dielectric layers in integrated circuits
US4642162A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 2, 1986 |
| Grant date | Feb 10, 1987 |
| Priority date | — |
| Expiry date | Jan 2, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31055
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is disclosed for the planarization of a semiconductor device structure by a two stage planarization process which comprises: applying a dielectric layer over a first conductive layer, spin coating an organic layer onto the first dielectric layer, etching the device in a plasma etching process to substantially remove the organic planarization layer, then etching the device in a plasma etching process which etches the exposed dielectric layer to substantially remove all of it, removing the remaining organic planarization layer, followed by the application of a second dielectric layer under bias sputter deposition conditions. The bias sputter deposition fills trenches and eliminates peaks in the remaining first dielectric layer as it builds up the second dielectric layer. The process planarizes the dielectric layer without thickness variations dependent upon conductor layer pattern density.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.