Noise reduction during testing of integrated circuit chips
US4644265A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 1985 |
| Grant date | Feb 17, 1987 |
| Priority date | — |
| Expiry date | Sep 3, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3193
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Disclosed is a test system having circuitry for reducing off-chip driver switching (delta I) noise. The test system employs a tester connected to and electrically testing an integrated circuit chip. The integrated circuit chip has a plurality of input terminals for receiving an electrical test pattern from the tester. The integrated circuit chip also includes a plurality of output driver circuits having outputs connected to the tester. The test system is characterized in that the integrated circuit chip includes a driver sequencing network under control of the tester for sequentially conditioning the off-chip driver circuits for possible switching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.