Method for making a self-aligned CMOS EPROM wherein the EPROM floating gate and CMOS gates are made from one polysilicon layer

US4646425A · kind A · utility

Assignee

• Solid State Scientific Corporation · US

Inventors

• Alexander H. Owens · Los Gatos, US
• Mark A. Halfacre · Horsham, US
• David S. Pan · Doylestown, US

Key dates

• Filing date: Dec 10, 1984
• Grant date: Mar 3, 1987
• Expiry date: Dec 10, 2004

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B41/49

Abstract

A CMOS EPROM is made wherein the typical EPROM device is an N-channel IGFET having a control gate self-aligned with an underlying floating gate. In this process the EPROM floating gate and the gates of both the P-channel and N-channel peripheral circuit transistors are formed from a first deposited polysilicon layer. The EPROM control gate is formed from a second deposited polysilicon layer. This CMOS EPROM process employs a surprisingly few photoresist steps and is compatible with a high temperature oxidation step for making a very high quality intergate polysilicon oxide in the EPROM devices.