Fabrication process employing special masks for the manufacture of high speed bipolar analog integrated circuits
US4648909A · kind A · utility
13Cited by
13References
24Claims
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Key dates
| Filing date | Nov 28, 1984 |
| Grant date | Mar 10, 1987 |
| Priority date | — |
| Expiry date | Nov 28, 2004 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fabrication process for integrated circuits having linear bipolar transistors and other circuit elements. The process defines collector contact 32, base 34, and isolation 36 regions in one masking operation. Subsequent masking layers of photoresist 40, 42, 46 are used to shield selected regions during implantation of exposed regions. Circuit density is improved through the use of aluminum doped isolation regions 36. The base region is doped in a single ion implantation step, which is followed by low temperature deposition of a covering oxide layer 48.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.