Method and apparatus for fault tolerant serial communication of digital information
US4649384A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 1983 |
| Grant date | Mar 10, 1987 |
| Priority date | — |
| Expiry date | Oct 7, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for serial communication of digital information in an information processing system for high throughput fault tolerant communication is disclosed. High throughput is achieved by providing a multiplicity of communication circuits, which are preferably four-wire, full duplex bidirectional channels for serial communication of digital information, and by providing full duplex, bidirectional communication of messages at a first rate and half duplex, unidirectional communication of large blocks of data at a second higher rate over the communication circuits. Fault tolerance for serial communication of digital information is provided by the multiplicity of communication circuits so that if one communication circuit is inoperative the remainder of the communication circuits is available for communication. The method and apparatus facilitate circuit implementation of an architecture for high throughout fault tolerant serial communication of digital information in a loosely coupled information processing system. Other features are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.