Stephen James Sheafor
27Patents
7h-index
21Co-inventors
69Inventor score
Filing activity: Oct 7, 1983 → May 24, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6223242A | Linearly expandable self-routing crossbar switch | Electricity | 46 | Expired |
| US5983303A | Bus arrangements for interconnection of discrete and/or integrated modules in a digital system and associated method | Physics | 45 | Expired |
| US4649384A | Method and apparatus for fault tolerant serial communication of digital information | Physics | 30 | Expired |
| US6088753A | Bus arrangements for interconnection of discrete and/or integrated modules in a digital system and associated method | Physics | 22 | Expired |
| US6119188A | Priority allocation in a bus interconnected discrete and/or integrated digital multi-module system | Physics | 14 | Expired |
| US6321285A | Bus arrangements for interconnection of discrete and/or integrated modules in a digital system and associated method | Physics | 14 | Expired |
| US6311244A | Priority allocation in a bus interconnected discrete and/or integrated digital multi-module system | Physics | 7 | Expired |
| US10096354B1 | SRAM with error correction in retention mode | Physics | 5 | Active |
| US6493407B1 | Synchronous latching bus arrangement for interfacing discrete and/or integrated modules in a digital system and associated method | Physics | 3 | Expired |
| US7386028B2 | Reduced EMI device and method thereof | Electricity | 3 | Expired |
| US9880583B2 | Low power autonomous peripheral management | Emerging Cross-Sectional Technologies | 2 | Active |
| US10319429B2 | SRAM with error correction in retention mode | Physics | 2 | Active |
| US6473813B1 | Module based address translation arrangement and transaction offloading in a digital system | Physics | 2 | Expired |
| US10788884B2 | Very low power microcontroller system | Emerging Cross-Sectional Technologies | 2 | Active |
| US10754414B2 | Very low power microcontroller system | Emerging Cross-Sectional Technologies | 2 | Active |
| US8924765B2 | Method and apparatus for low jitter distributed clock calibration | Electricity | 1 | Active |
| US9772648B2 | Low power asynchronous counters in a synchronous system | Emerging Cross-Sectional Technologies | 1 | Active |
| US10416703B2 | Counter/timer array for generation of complex patterns independent of software control | Electricity | 1 | Active |
| US10629257B2 | SRAM with error correction in retention mode | Physics | 1 | Active |
| US11822364B2 | Very low power microcontroller system | Emerging Cross-Sectional Technologies | 1 | Active |
| US10795425B2 | Very low power microcontroller system | Emerging Cross-Sectional Technologies | 1 | Active |
| US9703313B2 | Peripheral clock management | Emerging Cross-Sectional Technologies | 0 | Active |
| US10585448B2 | Low power autonomous peripheral management | Emerging Cross-Sectional Technologies | 0 | Active |
| US10885972B2 | SRAM with error correction in retention mode | Physics | 0 | Active |
| US9939839B2 | Low power automatic calibration method for high frequency oscillators | Emerging Cross-Sectional Technologies | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.