Multiple port memory with port decode error detector
US4649475A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 2, 1984 |
| Grant date | Mar 10, 1987 |
| Priority date | — |
| Expiry date | Apr 2, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved multiple port memory system has a priority network for selecting between multiple units seeking access thereto. The priority network responds to requests for access and provides encoded port identifying signals indicative of the port to have access. Decode circuitry decodes the encoded port identifying signals and provides unique port enabling signals for the selected port. Decode error detection circuitry responds to the decoded port enabling signals and provides a decode error indication any time multiple port enabling signals are detected as occurring simultaneously. Port Code error detecting circuitry respond to the encoded port identifying signals and the decoded port enabling signals to provide a code error indicating signal when a port code error condition is detected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.