Forming memory transistors with varying gate oxide thicknesses
US4651406A · kind A · utility
147Cited by
8References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 4, 1986 |
| Grant date | Mar 24, 1987 |
| Priority date | — |
| Expiry date | Jun 4, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit device and a method of manufacturing the same, wherein an MIS type memory transistor of a two-layered gate electrode structure is formed on the surface of a semiconductor substrate, and an MIS type transistor for a low voltage having a comparatively thin gate oxide film and an MIS type transistor for a high voltage having a comparatively thick gate oxide film are formed around the memory transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.