Fabrication of stacked MOS devices utilizing lateral seeding and a plurality of separate implants at different energies
US4651408A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 1984 |
| Grant date | Mar 24, 1987 |
| Priority date | — |
| Expiry date | May 17, 2004 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/164
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a process for manufacturing vertically integrated MOS devices and circuits, gate oxide and a gate are formed on a semiconductor substrate such as a silicon substrate. A layer of polysilicon is then deposited over the wafer, the polysilicon contacting the substrate silicon through a window in the gate oxide. The substrate silicon and the polysilicon are then laser melted and cooled under conditions that encourage crystal seeding from the substrate into the polysilicon over the gate. Subsequently, ions are implanted into the silicon substrate and the polysilicon to form source and drain regions. By introducing the source and drain dopants after melt associated seeding of the polysilicon, the risk of dopant diffusion into the device channel regions is avoided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.