Patent · US Expired

Method of making and selectively doping isolation trenches utilized in CMOS devices

US4653177A · kind A · utility

31Cited by
12References
6Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJul 25, 1985
Grant dateMar 31, 1987
Priority date—
Expiry dateJul 25, 2005

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L21/0337
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

It is known to utilize dielectric-filled trenches in a CMOS integrated-circuit device to achieve electrical isolation between adjacent n-channel and p-channel regions. In that way, latchup-free operation of the device is ensured. But inversion effects along the walls of the trenches can cause high leakage currents, undesirably high parasitic capacitances and even shorting together of source/drain regions. In accordance with the invention, a nonlithographic technique including selective anodic oxidation is employed to selectively mask the sidewalls of the trenches. Each sidewall can then be independently doped thereby effectively eliminating the possibility of inversion occurring therealong.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.