Process for patterning local interconnects
US4657628A · kind A · utility
183Cited by
2References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 7, 1986 |
| Grant date | Apr 14, 1987 |
| Priority date | — |
| Expiry date | Mar 7, 2006 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/911
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A local interconnect system for VLSI integrated circuits. After titanium is deposited for self-aligned silicidation of exposed moat and gate regions in a nitrogen atmosphere, a hardmask is deposited and patterned over the titanium. When a conductive titanium nitride layer is formed overall, it will already be patterned according to this hardmask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.